1. Field of the Invention
The present invention relates generally to electrical circuits, more specifically to integrated circuit (xe2x80x9cICxe2x80x9d) buffers, and more particularly to a high speed complementary metal oxide silicon (xe2x80x9cCMOSxe2x80x9d) buffer with monotonic hysteresis capable of working with a very low power supply voltage (xe2x80x9cVccxe2x80x9d), yet having a small trip point range.
2. Description of Related Art
A Schmitt Trigger is an electronic circuit well known in the state of the art and often used to turn a signal having a slow or asymmetrical transition into a signal with a sharp transition region. Schmitt Triggers are useful of IC inputs to clean up input change signals and to do signal level transitions. However, a Schmitt Trigger is generally slower than an inverter circuit of the same operational power. Moreover, a Schmitt trigger uses more current because several wide, big, integrated circuit elements are simultaneously in an ON-state for a relatively long time period. In practice they are not easily optimized for high speed circuitry and they do not provide a xe2x80x9cmonotonicxe2x80x9d hysteresis (never increasing nor decreasing as independent variables increase or decrease) over a wide range of integrated circuit power supply potential, Vcc, range (e.g., about 1.4-volts to 3.6-volts); the lower the Vcc, the worse the performance. In fact, in the state of the art of IC design the call for lower power consumption in much denser IC chip designs is constant; Vcc is being reduced at a much faster rate than in the past.
FIG. 1 (Prior Art) is an electrical schematic for a conventional Schmitt Trigger. Four, stacked, parallel input, metal-oxide-silicon field effect transistors (xe2x80x9cMOSFETxe2x80x9d) P1, P2, N1, and N2 are coupled by their respective gate electrodes to the trigger input (xe2x80x9cINxe2x80x9d); respective source/drain electrodes are connected in series. Based on the transition of the signal IN, one of the pair will generate a signal (xe2x80x9cVfpxe2x80x9d or xe2x80x9cVfnxe2x80x9d where xe2x80x9cVfxe2x80x9d is determined by the transistor size ratio P3/P1 and N3/N1) to the related respective output transistor P3 or N3, connected to generate the output signal xe2x80x9cOUTxe2x80x9d having a sharp, clean transition between levels. In operation, if the output node, OUT, is low, then the p-channel output transistor P3 is ON and the n-channel output transistor N3 is OFF; the p-channel input transistors P2, P3 dictate the trip point. If the output is HIGH, the output n-channel transistor N3 is ON and the p-channel output transistor P3 is OFF; the n-channel input transistors N2, N3 dictate the trip point; and, p-channel input transistors P1, P2 are ON, providing a direct current (xe2x80x9cDCxe2x80x9d) path to Vcc. Assuming that OUT is HIGH and that IN is LOW, the n-channel input transistors N1 and N2 are OFF and the n-channel output transistor N3 is ON. The node at Vfn floats to Vfn=Vcc-Vtn, where Vt is transistor turn-on voltage; thus, If the IN signal has a voltage, Vin, less than the Vtn of the n-channel input transistor N1 (Vin less than Vtn1), Vfn remains at Vcc14 Vtn. As Vin increases, n-channel input transistor N1 begins to turn on and Vfn starts to fall toward Vss, where Vss is zero volts. The trip point is defined when Vin=Vtn2+Vfn, that is, when n-channel input transistor N2 starts to turn ON. As the second n-channel input transistor N2 turns ON, the output starts to move toward Vss, causing the n-channel output transistor N3 to start turning OFF. In turn, this causes Vfn to fall, turning the n-channel input transistor N2 further toward its ON state. This continues until the n-channel output transistor N3 is totally OFF and both n-channel input transistors N1, N2 are totally ON. This xe2x80x9cpositive feedbackxe2x80x9d causes the trip point to be well defined. At the HIGH trip point Vfn=Vtrip-Vtn. Since the n-channel input transistor N2 is used as a switch, it has a size much bigger than the other n-channel transistor N1. This inherently makes the switching slower. (A similar analysis applies to the p-channel side of this Schmitt Trigger when IN is HIGH and OUT is LOW). By its design, it is not adaptable to high speed functionality since effective switching resistances of MOSFETS are difficult to reduce without changing the trip point. The circuit hysteresis is dependent on Vcc and at very low Vcc levels does not work properly.
FIG. 2 shows a more compact circuit design for another conventional Schmitt Trigger. A basic inverter latch circuit is employed in which two series connected transistor pairs P1/N1 and P2/N2 provide a higher speed performance. However, the switching point voltages of this circuit design are more difficult to predict, especially with respect to keeping a monotonic hysteresis over a wide range of Vcc. Input transistors P1 and N1 size ratio dictates the nominal trip point. The input transistors P1, N1 are relatively large devices for speed, having relatively short channel lengths; whereas, output transistors P2, N2 are relatively small devices with relatively long channel lengths. When IN is LOW, the first stage output, xe2x80x9cOUTA,xe2x80x9d is HIGH and the second stage output, xe2x80x9cOUTB,xe2x80x9d is LOW, turning the p-channel output transistor P2 ON. As the input rises, the n-channel input transistor N1 has to overcome not only the bias of the p-channel input transistor P1 where Vgs (xe2x80x9cgate-sourcexe2x80x9d) is reducing, but also a weak sized p-channel output transistor P2 where Vgs=Vcc. When IN is going HIGH to LOW, initially OUTA is LOW and OUTB is HIGH. MOSFET N2 is ON and MOSFET P2 is OFF. MOSFET P1 starts to turn ON and has to overcome MOSFET N2 where Vgs=Vcc and MOSFET N1. Thus, the main P1/N1 inverter has to fight P2/N2 reducing transition speed substantially. While this circuit is faster than that shown in FIG. 1, there are substantive fabrication issues. The mismatch in size between the input and output transistors relates directly to a mismatch in respective Vt; this causes more process variations on the trip points and hysteresis characteristic. Again, with a wide range Vcc designs, the hysteresis is not monotonic and trip points are difficult to define.
There is a need to have an IC input buffer design adaptable to a supply voltage which can vary in order to provide a common interface at the chip boundary. The input buffer design should provide relatively high speed (that is, have a low signal propagation delay time) have a hysteresis that is relatively independent of process Vcc and is substantially monotonic regardless of Vcc change.
In its basic aspects, the present invention provides a CMOS Schmitt Trigger device including: an input stage forming an inverter, having a pair of input stage CMOS devices, for receiving an input signal; and an output stage, having a first output stage device in parallel with the input stage, the first output stage device having a pair of first output stage CMOS devices coupled to the input stage CMOS devices such that the pair of second stage CMOS devices add to the respective input stage CMOS devices only one at time for changing the trip point of the Schmitt Trigger device, and having a second output stage device connected to the first output stage device for driving an output node.
In another aspect, the present invention provides an integrated circuit buffer device having a circuit input node and a circuit output node, including: connected to the circuit input node, an inverter circuit first stage having a first trip point; connected to the inverter circuit first stage, an inverter circuit second stage wherein said second stage is additive to said inverter circuit first stage for changing said trip point and wherein said first stage and said second stage are connected in parallel having a first output node; an inverter connecting said first output node to said circuit output node; and connected in series to the inverter circuit second stage, a output stage device connected to the circuit output node, wherein said output stage device has discrete component sizes substantially greater than discrete component sizes of the inverter circuit first stage and second stage such that a substantially monotonic hysteresis characteristic and tight trip point tolerance is established for said buffer device.
In yet another aspect, the present invention provides an integrated circuit having an input buffer having a plurality of Schmitt Trigger circuits, each of said Trigger circuits including: a trigger input node; coupled to the trigger input node, a first stage CMOS inverter having a first p-channel MOSFET and a first n-channel MOSFET, wherein size ratio of the input stage first p-channel MOSFET to first n-channel MOSFET determines a trip point of the first stage; coupled to the first stage CMOS input inverter, a second stage CMOS inverter having a second p-channel MOSFET and a second n-channel MOSFET, wherein a ratio of first stage MOSFET size to second stage MOSFET size determines trip point of the Schmitt Trigger device, said second stage having a second stage output node; a trigger output node; an inverter coupling the second stage output node to the trigger output node; and coupled to the second stage CMOS inverter and to said trigger output node, a CMOS output stage, wherein said output stage has discrete component sizes substantially greater than discrete component sizes of the inverter first stage and second stage, wherein a substantially monotonic hysteresis characteristic and tight trip tolerance is established for each of said Schmitt Trigger circuits.
Some of the advantages of the present invention are:
it provides a relatively high speed CMOS input buffer design;
it provides a Schmitt Trigger which has a hysteresis that is substantially monotonic with Vcc changes;
the resultant circuit has a hysteresis that is fabrication process independent;
it provides a predictable Schmitt trigger adaptable to very low power supply voltage circuits; and
it provides a Schmitt trigger that has less trip point variation; in other words, the trip point range tolerance is tighter.
The foregoing summary and list of advantages is not intended by the inventors to be an inclusive list of all the aspects, objects, advantages and features of the present invention nor should any limitation on the scope of the invention be implied therefrom. This Summary is provided in accordance with the mandate of 37 C.F.R. 1.73 and M.P.E.P. 608.01 (d) merely to apprise the public, and more especially those interested in the particular art to which the invention relates, of the nature of the invention in order to be of assistance in aiding ready understanding of the patent in future searches. Other objects, features and advantages of the present invention will become apparent upon consideration of the following explanation and the accompanying drawings, in which like reference designations represent like features throughout the drawings.